Semiconductors and integrated circuit chips have become ubiquitous within many products due to their continually decreasing cost and size. In the microelectronics industry as well as in other industries involving construction of microscopic structures (e.g., micromachines, magnetoresistive heads, etc.) there is a continued desire to reduce the size of structural features and microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (more processing per clock cycle and less heat generated) at lower power levels and lower cost. Present technology is at or approaching atomic level scaling of certain micro-devices such as logic gates, FETs and capacitors, for example. Circuit chips with hundreds of millions of such devices are not uncommon. Further size reductions appear to be approaching the physical limit of trace lines and micro-devices that are embedded upon and within their semiconductor substrates. The present invention is directed to such micro-sized devices.
Basically, a FET is a transistor having a source, a gate, and a drain. The action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, is controlled by the transverse electric field under the gate.
As known to those skilled in the art, P-type FETs (PFETs) turn ON to allow current flow from source to drain when the gate terminal is at a low or negative potential with respect to the source. When the gate potential is positive or the same as the source, the P-type FET is OFF, and does not conduct current. On the other hand, N-type FETs (NFETs) turn ON to allow current flow from source to drain when the gate terminal is high or positive with respect to the source. When the gate potential is negative or the same as the source, the N-type FET is OFF, and does not conduct current. Note that in each of these cases there is a threshold voltage (e.g., at the gate terminal) for triggering actuation of the FET.
More than one gate (multi-gate) can be used to more effectively control the channel. The length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (i.e., the distance between the source and drain). Multi-gate FETs are considered to be promising candidates to scale complementary metal-oxide semiconductor (CMOS) FET technology down to the sub-22 nm regime. However, such small dimensions necessitate greater control over performance issues such as short channel effects, punch-through, metal-oxide semiconductor (MOS) leakage current and, of particular relevance herein, the parasitic resistance that is present in a multi-gate FET.
The size of FETs has been successfully reduced through the use of one or more fin-shaped channels. A FET employing such a channel structure may be referred to as a FinFET. Previously, CMOS devices were substantially planar along the surface of the semiconductor substrate, the exception being the FET gate that was disposed over the top of the channel. Fins break from this paradigm by using a vertical channel structure in order to maximize the surface area of the channel that is exposed to the gate. The gate controls the channel more strongly because it extends over more than one side (surface) of the channel. For example, the gate can enclose three surfaces of the three-dimensional channel, rather than being disposed only across the top surface of the traditional planar channel.
One technique for affecting the threshold voltage (e.g., increasing the threshold voltage, encouraging a more constant threshold voltage over different gate lengths) is to use locally implanted dopants under the gate edge(s). This is referred to as a “halo” implant. As non-limiting examples, the halo implant may include arsenic, phosphorous, boron and/or indium.
Silicon-on-insulator (SOI) wafers have been used to exploit the improved quality of monocrystalline silicon provided thereby in an active layer formed on an insulator over a bulk silicon “handling” substrate. Similar attributes can be developed in similar structures of other semiconductor materials and alloys thereof. The improved quality of the semiconductor material of the active layer allows transistors and other devices to be scaled to extremely small sizes with good uniformity of electrical properties.
Unfortunately, the existence of the insulator layer which supports the development of the improved quality of semiconductor material also presents a problem known in the art as floating body effect in transistor structures. The floating body effect is specific to transistors formed on substrates having an insulator layer. The neutral floating body is electrically isolated by source/drain and halo extension regions that form oppositely poled diode junctions at the ends of the transistor conduction channel and floating body while the gate electrode is insulated from the conduction channel through a dielectric. The insulator layer in the substrate completes insulation of the conduction channel and thus prevents discharge of any charge that may develop in the floating body. Charge injection into the neutral body when the transistor is not conducting develops voltages in the conduction channel in accordance with the source and drain diode characteristics.
The voltage developed due to charge collection in the channel has the effect of altering the switching threshold of the transistor. This effect, in turn, alters the signal timing and signal propagation speed since any transistor will have a finite slew rate and the rise and fall time of signals is not instantaneous even when gate capacitance is very small. Therefore, the diode characteristics of the source and drain can be tailored to limit charge build-up in the floating body.
To do so, the diode junctions can be made somewhat leaky to allow the floating body of the transistor to be discharged to an acceptable degree. Unfortunately, since FETs are often formed symmetrically with similar or identical source and drain impurity structures, development of such a characteristic reduces the ratio of resistance of the “ON” and “OFF” states of the transistor, often referred to as the on/off ratio. A large on/off ratio is generally desirable to support maximum circuit fanout (the number of transistor gates a transistor can drive with acceptable switching speed) and to provide maximum signal voltage swing close to the power supply voltage. Therefore, there is a trade-off between limitation of floating body effects and maintaining a suitable on/off ratio.
One approach to reduction of floating body effects is to use body contacts to form a connection from the floating body/conduction channel to the source electrode through the impurity well. In some cases, the body contact effectively ties the body of the FET to ground. This approach is only a partial solution since the well can be highly resistive and the connection can be ineffective. Further, the connection requires additional chip space and, therefore, may affect or preclude achievement of the potential integration density that would otherwise be possible. This type of device may be referred to as a “body-tied” FET, and may be P-type or N-type.
While many designs for FETs are symmetrical, the use of asymmetric devices (e.g., asymmetric or asymmetrical FETs or MOSFETs) has become prevalent, for example, in SOI CMOS technologies. In such asymmetric devices there is a preferred direction for majority charge carrier flow. As an example, this preference may be due to different dopings of or in relation to (i.e., relative to) the source and drain regions, such as different implant dosages or asymmetric implant(s) (e.g., asymmetric source and/or drain extension implants, asymmetric halo implants) relative to the gate channel conductor. Asymmetric devices can provide advantages of increased drive currents and reduced parities. As a non-limiting example, asymmetric extension and halo devices can be fabricated by using angled implants and by using the (possibly dummy) gate to mask the source or drain region (e.g., due to shadowing by the gate structure).
However, a problem arises in scaling these asymmetric devices to groundrules associated with 45 nm technologies and beyond. In that these devices typically offer a significant performance increase (e.g., about 7-15%) from both floating body control and Miller capacitance reduction, the potential loss of this performance for future CMOS technology presents a significant impediment to future development.